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List of  Publications

Journal Papers:

1. M. Jagadesh Kumar and Vinod Parihar, "Realizing high current gain PNP transistors using a novel Surface Accumulation Layer Transistor (SALTran) concept," To appear in  IEE Proceedings - Circuits, Devices and Systems, Vol.151,  2004.

2.G.Venkateshwar Reddy and M. Jagadesh Kumar,"A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET  Two-dimensional Analytical Modeling and Simulation," To appear in  IEEE Trans. on Nanotechnology, 2004.

3. M. Jagadesh Kumar and G.Venkateshwar Reddy, "Evidence for suppressed Short-channel effects in deep Submicron Dual-Material Gate (DMG) Partially Depleted SOI MOSFETs A Two-dimensional Analytical Approach,"  To appear in Microelectronic Engineering, 2004.

4. Anurag Chaudhry and M. Jagadesh Kumar,"Investigation of the Novel Attributes of a Fully Depleted (FD) Dual-Material Gate (DMG) SOI MOSFET,"   IEEE Trans. on Electron Devices, Vol.15, September 2004.

5. G.Venkateshwar Reddy and M. Jagadesh Kumar, "Investigation of the Novel Attributes of a Single-Halo Double Gate SOI MOSFET: 2D Simulation Study," Microelectronics Journal, Vol.35, pp.761-765, September 2004

6. M. Jagadesh Kumar and Vinod Parihar,, "Surface Accumulation Layer Transistor (SALTran): A New Bipolar Transistor for Enhanced Current Gain and Reduced Hot-carrier Degradation," To appear in IEEE Trans. on Device and Materials Reliability, Vol.4, 2004.

7. Meena Mishra, M. Jagadesh Kumar, Yashvir Singh, S.R.Shukla, H.P.Vyas, D.S.Rawal, A.Naik, H. S. Sharma, B. K.Sehgal and R.Gulati, "Inverse Modeling of Delta Doped PHEMTs,"  Journal of Vacuum Science & Technology A-Vol.22(3), pp.1036-1039, May-June 2004

8. M. Jagadesh Kumar and Anurag Chaudhry, "Two-Dimensional Analytical Modeling of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET and Evidence for Diminished Short-Channel Effects", IEEE Trans. on Electron Devices, Vol.15, pp.569-574, April 2004.

9. Anurag Chaudhry and M. Jagadesh Kumar, "Controlling Short-channel Effects in Deep Submicron SOI MOSFETs for Improved Reliability: A Review", IEEE Trans. on Device and Materials Reliability, Vol.4, pp.99-109, March 2004.

10. M. Jagadesh Kumar and D. Venkatesh Rao, "Proposal and Design of a New SiC-Emitter Lateral NPM Schottky Collector Bipolar Transistor (SCBT) on SOI for VLSI Applications," IEE Proceedings - Circuits, Devices and Systems, Vol.151, pp.63-67, February 2004.

11. M. Jagadesh Kumar and C. Linga Reddy, "Realizing wide bandgap P-SiC-emitter Lateral Heterojunction Bipolar Transistors with Low Collector-Emitter Offset Voltage and High Current Gain-A Novel Proposal using Numerical Simulation," IEE Proceedings - Circuits, Devices and Systems, Vol.151, April 2004.

12. M. Jagadesh Kumar and C. Linga Reddy, "A New High Voltage 4H-SiC Lateral Dual Sidewall Schottky (LDSS) Rectifier: Theoretical Investigation and Analysis", IEEE Trans. on Electron Devices, Vol.50, pp.1690-1693, July 2003.

13. M. Jagadesh Kumar and C. Linga Reddy, "2D-Simulation and Analysis of Lateral SiC N-emitter SiGe P-base Schottky Metal-collector (NPM) HBT on SOI", Microelectronics Reliability, Vol.43, pp.1145-1149, July 2003..

14. M. Jagadesh Kumar and Vikram Verma, "Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFETs," IEEE Trans. on Reliability, Vol.51, pp.367-370, September 2002. (Citation - 1 time)

15. M. Jagadesh Kumar and Yashvir Singh, " A New Low-loss Lateral Trench Sidewall Schottky (LTSS) Rectifier on SOI with High and Sharp Breakdown Voltage," IEEE Trans. on Electron Devices, Vol.49, pp.1316-1319, July 2002.

16. M. Jagadesh Kumar and D. Venkatesh Rao, " A New Lateral PNM Schottky Collector Bipolar Transistor (SCBT) on SOI for Non-saturating VLSI Logic Design," IEEE Trans. on Electron Devices, Vol.49, pp.1070-1072, June  2002.

17. Yashvir Singh and  M. Jagadesh Kumar, "Lateral Thin Film Schottky (LTFS) Rectifier on SOI: A Device with Higher than Plane Parallel Breakdown Voltage,"   IEEE Trans. on Electron Devices, Vol.49, pp.181-184,  January 2002. Read the Paper

18. Yashvir Singh and  M. Jagadesh Kumar,  "A New 4H-SiC Lateral Merged Double Schottky (LMDS) Rectifier with Excellent Forward and Reverse Characteristics,"   IEEE Trans. on Electron Devices,  Vol.48, pp.2695-2700, December 2001. Read the Paper

19. M. Jagadesh Kumar and V.S.Patri, "On the iterative schemes to obtain base doping profiles for reducing  base transit time in a bipolar transistor," IEEE Trans. on Electron Devices, vol.48,  pp.1222-1224, June 2001.(Citation -  1 time) Read the Paper

20. Yashvir Singh and  M. Jagadesh Kumar,  "Novel Lateral Merged Double Schottky (LMDS) Rectifier: Proposal and Design," IEE Proceedings - Circuits, Devices and Systems, Vol.148, No.3, pp.165-170, June, 2001.   Read the Paper

21. Vikram Verma and M. Jagadesh Kumar, "Study of the extended P+ dual source structure for eliminating bipolar induced breakdown in submicron SOI MOSFETs," IEEE Trans. on Electron Devices, Vol.47, pp.1678-1680, August, 2000. Read the Paper

22. V.S.Patri and M. Jagadesh Kumar, " Novel Ge profile design for high speed SiGe HBTs: Modeling and analysis," IEE Proceedings - Circuits, Devices and Systems, vol.146, pp.291-296, October 1999. Read the Paper (Citation -  1 time)

23. K. Dutta and M. Jagadesh Kumar, "A simple hole scattering length model for the solution of charge transport in bipolar transistors," IEEE Trans. on Electron Devices, vol.46, pp.1186-1188, June 1999. Read the Paper

24. V.S.Patri and M. Jagadesh Kumar, "Profile design considerations for minimizing the base transit time in SiGe HBTs," IEEE Trans. on Electron Devices, vol.45, pp.1725-1732, August 1998.(Citation -  6 times) Read the Paper

25. M. Jagadesh Kumar and K.Dutta, "Miller's approximation in VLSI and power bipolar transistors with reach-through collectors," IEEE Trans. on Electron Devices, vol.44, pp.2305-2307, December 1997. (Citation -  1 time) Read the Paper

26. M. Jagadesh Kumar and K. Dutta, "Optimum collector width of VLSI bipolar transistors for maximum   fmax at high current densities," IEEE Trans. on Electron Devices, vol.44, pp.903-905, May 1997. (Citation - 1 time) Read the Paper

27. K. Dutta and M. Jagadesh Kumar, "  Cjc  and the output conductance of advanced bipolar junction transistors under non-local impact ionization conditions," Solid-state Electronics, vol.39, no.12, pp.1819-1821, December 1996. (Citation - 1 time) Read the Paper

28. M. Jagadesh Kumar and S.G.Chamberlain, "Selective reactive ion etching of PECVD silicon nitride over amorphous silicon in CF4/H2 and nitrogen containing CF4/H2 plasma gas mixtures," Solid-state Electronics, vol.39, no.1, pp.33-37, January 1996. (Citation - 2 times) Read the Paper

29. M. Jagadesh Kumar and D.J.Roulston, "New buried P+ grid polyemitter bipolar transistor,"  Solid-state Electronics, vol.38, no.10, pp.1854-1856, October 1995. Read the Paper

30. M. Jagadesh Kumar and D.J.Roulston, "Design trade-offs for VCE(sat)-IC of bipolar transistors under forced gain conditions," IEEE Trans. on Electron Devices, vol.41, pp.378-403, No.3, March 1994. Read the Paper

31. M. Jagadesh Kumar and D.J.Roulston, "Miller's approximation in advanced bipolar transistors under non-local impact ionization conditions," IEEE Trans. on Electron Devices, vol.41, No.12, pp.2471-2473, December 1994.(Citation - 2 time) Read the Paper

32. M. Jagadesh Kumar and D.J. Roulston, "Base etched self-aligned transistor technology for advanced polyemitter bipolar transistors," IEE Electronics letters, vol.30, No.10, pp.819-820, May 1994. Read the Paper

33. M. Jagadesh Kumar and D.J.Roulston, "Optimum collector design of advanced bipolar transistors for high speed and high current operation," Solid-state Electronics, vol.37, No.11, pp.1885-1887, November 1994.

34. M. Jagadesh Kumar, A.D.Sadavnikov and D.J.Roulston, "Collector design trade-offs for low voltage applications of advanced bipolar transistors," IEEE Trans. on Electron Devices, vol.40, pp. 1478-1483, No.8, August 1993. (Citation - 5 times)   Read the Paper

35. M. Jagadesh Kumar and K.N.Bhat, "Collector recombination lifetime from the quasi-saturation analysis of high voltage bipolar transistors," IEEE Trans. on Electron Devices, vol.37, pp. 2395-2398, November 1990. (Citation - 3 times) Read the Paper

36. M. Jagadesh Kumar and K.N.Bhat, "The effects of emitter region recombination and bandgap narrowing on the current gain and the collector lifetime of high voltage bipolar transistors," IEEE Trans. on Electron Devices, vol.36, pp. 1803-1810, September 1989. (Citation - 13 times) Read the Paper

37. K.N.Bhat, M. Jagadesh Kumar et. al., "The effects of collector lifetime on the characteristics of high voltage bipolar transistors operating in the quasi-saturation region," IEEE Trans. on Electron Devices, vol.34, pp. 1163-1169, May 1987. (Citation -5 times)

38. M. Jagadesh Kumar, C.R.Selvakumar, V.Ramamurthy and K.N.Bhat, "On the dominant recombination level of platinum in silicon," Physica Status Solidi(a), vol.87, pp. 651-655, February 1985. (Citation - 5 times)

Conference Publications:

39. M. Jagadesh Kumar and Vinod Parihar, "Enhanced Current Gain in SiC Power BJTs Using Surface Accumulation Layer Transistor (SALTran) Concept," Accepted for  presentation in  IEEE TENCON'04 To be held at Chiang Mai, Thailand, Nov 21-24, 2004.

40. M. Jagadesh Kumar and G. Venkatesh Reddy, "Analytical Model for the Threshold Voltage of  Dual Material Gate (DMG) Partially Depleted SOI MOSFET and Evidence for Reduced Short-channel Effects," The 7th International Conference on Solid-State and Integrated-Circuit Technology(ICSICT-04), October 18-21, 2004 Beijing, China
41. Anurag Chaudhry and M. Jagadesh Kumar, "Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET using Two-Dimensional Numerical Simulation Studies" VLSI Design, 2004. Proceedings. 17th International Conference on , pp.662 - 665, 5-9 Jan. 2004

42. M. Jagadesh Kumar and Vinod Parihar, A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors," VLSI Design, 2004. Proceedings. 17th International Conference on , pp.827-831, 5-9 Jan. 2004

43. G.Venkateshwar Reddy and M. Jagadesh Kumar, "A New Dual-Material-Double-Gate (DMDG) SOI MOSFET for Nanoscale CMOS Design", 2003 International Semiconductor Device Research Symposium (ISDRS), pp.238-239, Washington DC, USA, December 10-12, 2003.

44. M. Jagadesh Kumar and Vinod Parihar, "A Novel High Current Gain Lateral PNP Transistor on SOI for Complimentary Bipolar Technology," 2003 International Semiconductor Device Research Symposium (ISDRS), pp.268-269, Washington DC, USA, December 10-12, 2003.

45. M. Jagadesh Kumar and Anurag Chaudhry, (Invited talk )" Two-dimensional Analytical Analysis of Short-channel Effects in Dual-Material Gate (DMG) SOI MOSFETs for sub-100 nm CMOS technology " Proceedings of 12th International Workshop on the Physics of Semiconductor Devices, pp.509-514, IIT Chennai, December 2003.

46. M. Jagadesh Kumar and Sukhendu Deb Roy, "A Novel Collector-tub Concept for realizing High-voltage Lateral Bipolar Transistors on SOI", 16th international Conference on Microelectronics, Cairo, Egypt, Dec 9-11, 2003.

47. M. Mishra, Y. Singh, S.S. Islam, S.R. Shukla, M.Jagadesh Kumar, A. Naik, B.K. Sehgal, R. Gulati, H.P. Vyas, "Inverse Modeling of Delta-doped PHEMTs", Eleventh Canadian Semiconductor Technology Conference, (CSTC), Ottawa, Canada, 18-22 August 2003.

48. M. Jagadesh Kumar and C. Linga Reddy, "A New dual-bandgap SiC-on-Si P-emitter, SiGe N-base, lateral Schottky Metal-collector (PNM) HBT on SOI with reduced collector-emitter offset-voltage" Proceedings of IEEE TENCON'03, pp.493-496, October 14-17, 2003.

49. M. Jagadesh Kumar and C. Linga Reddy, "A Novel 4H-SiC Lateral Dual Sidewall Schottky (LDSS) rectifier with excellent forward and reverse characteristics" IASTED International Conference on Circuits, Signals & Systems (CSS 2003), May 19 to May 21, 2003, in Cancun, Mexico.

50. M. Jagadesh Kumar and D. Venkatesh Rao, "A New SiGe Base Lateral PNM Schottky Collector Bipolar Transistor on SOI for Non-Saturating VLSI Logic Design," Proceedings of the 16th International Conference on VLSI Design(ISBN 0-7695-1868-0), pp:489-492, January 2003. Read the Paper

51. Y. Singh and M. Jagadesh Kumar, "A New Lateral Trench Sidewall Schottky Rectifier on SOI," Technical Proceedings of the NanoTech 2002 International Conference on Modeling and Simulation of Microsystems (ISBN:0-9708275-7-1), Vol.4, pp.592-595, San Juan, Puerto Rico, USA., April 22-25, 2002.

52. M. Jagadesh Kumar and Y. Singh (Invited Talk), "Lateral Schottky Rectifiers for Power Integrated Circuits," 11th International Workshop on the Physics of Semiconductor Devices, pp.414-421, December 2001.

53. Y. Singh and M. Jagadesh Kumar, "Low-loss High-performance Lateral Schottky Rectifiers on SOI," 11th International Workshop on the Physics of Semiconductor Devices, pp.1382-1385, December 2001.

54. Y. Singh, M. Jagadesh Kumar , S.R.Shukla, Meena Mishra, and H.P. Vyas, "Study of pseudomorphic HEMTs using 2D numerical simulation supported by experimental data," 11th International Workshop on the Physics of Semiconductor Devices, pp.1368-1371, December 2001.

55. M. Jagadesh Kumar (Invited talk), "SOI CMOS Circuits - Technology and Design Issues," Chandigarh Symposium on Microelectronics(CSME-2001), Punjab University, Chandigarh, Feb 16-17, 2001.

56. M. Jagadesh Kumar (Invited talk), "Design and modeling of SiGe HBT's for high frequency applications," 2nd National symposium on modeling of high frequency transistors, SPL, Delhi, 12 January 2001.

57. Y. Singh, M. Jagadesh Kumar , S.R.Shukla, Meena Mishra, and H.P.Vyas, "2D Simulations in Pseudomorphic HEMT's", 2nd National symposium on modeling of high frequency transistors, SPL, Delhi, 12 January 2001.

58. M. Jagadesh Kumar (Invited talk), "Floating Body Effects in submicron SOI MOSFETs," National Seminar on VLSI: Systems, Design and Technology, Electrical Engg Dept, Indian Institute of Technology, Mumbai, December 9-11, 2000.

59. M. Jagadesh Kumar (Invited talk), "Application of selectively delta-doped channel to control the floating body effect in submicron SOI MOSFETs," Proceedings of the Tenth International Workshop on the Physics of Semiconductor Devices, pp. December 1999.

60. M. Jagadesh Kumar and K. Dutta, "Analysis of ballistic hole transport in bipolar junction transistors," Proceedings of the Tenth International Workshop on the Physics of Semiconductor Devices, pp. December 1999.

61. M. Jagadesh Kumar and V.S.Patri, "Analysis of base Ge profile design in SiGe HBTs," Proceedings of the Tenth International Workshop on the Physics of Semiconductor Devices, Dec 14-Dec 18 1999. Published in Proceedings of SPIE - The International Society for Optical Engineering, Vol.3975, pp.422-425, 2000 ISSN: 0277-786X

62. V. S. Patri and M. Jagadesh Kumar, "Modeling and design of high speed SiGe HBTs for minimum base transit time" 85th Indian Science Congress, Osmania University, Hyderabad, January 1998.

63. M. Jagadesh Kumar, "Modeling the base transit time in SiGe HBTs for high speed operation," (Invited Talk), National symposium on modeling of high frequency transistors, SPL, Delhi, 7 November 1997.

64. M. Jagadesh Kumar and K. Dutta, "Validity of Miller's Approximation in Advanced Bipolar Transistors with Reach-through Collectors", 9th International Workshop on Physics of Semiconductor Devices, New Delhi, December 16-20, 1997.

65. M. Jagadesh Kumar and D. J. Roulston, ``Application of Polysilicon Emitter to High Voltage Transistors for Realizing High Quasi-saturation Current Limits Under Forced Gain Conditions," Proceedings of the 1993 Canadian IEEE Conference on Electrical & Computer Engineering, Vol.II, pp:798-801, Sept 14-17, 1993, Vancouver, British Columbia, Canada.

66. M. Jagadesh Kumar and K.N. Bhat, ``A Novel Method of Extracting the Collector Recombination Lifetime of High Voltage Bipolar Transistors", Fifth International Workshop on the Physics of Semiconductor Devices, New Delhi, December 21 - 26, 1989.

67. M. Jagadesh Kumar and K.N. Bhat, ``Modelling of the Current Gain and the Collector Lifetime of High Voltage Bipolar Transistors having Heavily Doped Emitters," Indian Vacuum Society  National Symposium on Vacuum Science and Technology, Department of Electrical Engineering, Indian Institute of Technology, Bombay, pp 145-156, December 19 - 21, 1988.

68. M. Jagadesh Kumar and K.N. Bhat, ``On the Bandgap Narrowing Models used in Bipolar Transistor Analysis", Proceedings (Contributed Papers) IV International workshop on the Physics of Semiconductor Devices, Madras, (India) pp. 145-147, December 1987.

69. M. Jagadesh Kumar, C.R. Selvakumar, V. Ramamurthy and K.N. Bhat, ``On the Compensation Effects of Platinum in Silicon", International Conference on the Physics and Technology of Compensated Semiconductors, Indian Institute of Technology, Madras, Abstracts pp 48-49, February 20-22, 1985.

70. M. Jagadesh Kumar and S. G. Chamberlain, ``Studies on Selective Reactive Ion Etching of PECVD Silicon Nitride and Amorphous Silicon for Applications in Thin Film Transistor Fabrication'', Internal Technical Report, SiDIC Laboratory, University of Waterloo, March 1994.

71. M. Jagadesh Kumar and S. G. Chamberlain, ``Development of the Plasma Enhanced Chemical Vapor Deposition for a-Si:H and Si_3N_4 on Large Area Glass Substrates,'' Internal Technical Report, SiDIC Laboratory, University of Waterloo, Waterloo, April 1994.