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Integrated Circuit Technology

Objective of the course:

This course aims at understanding the manufacturing methods and their underlying scientific principles in  the context of technologies used in VLSI chip fabrication.

Structure of the course:

Unlike in the traditional text-books, this course follows a top to bottom approach. Right in the beginning of the course, we study a complete process flow for both CMOS and advanced bipolar technologies. The idea is to introduce you at an early stage to the complexities and challenges associated with VLSI chip fabrication. Discussions on the  unit steps  will follow in greater detail  in the context of the complete CMOS and bipolar process flow.  It is expected that this will help you in gaining a better understanding  of both the constituent processes and the global picture of VLSI  manufacturing.

You are expected to participate in the class not only in terms of raising questions and answering them but also in terms of applying what you learn to contrived and real world problems.

Communicating with your teacher in the class is highly encouraged. Remember that many others in the class may have a similar (the so called trivial) doubt. So be brave and ask your questions.

Detailed Course Outline:

Introduction:  Historical Perspective and technology trends.   (1.5 lectures)

Modern CMOS Technologies: CMOS Process flow starting from Substrate selection to multilevel metal formation,  comparison between bulk and SOI CMOS technologies.  (3.5 Lectures)

Modern  Bipolar Technologies: Polysilicon Super Selfaligned Transistor Technology, Selective epitaxial growth technology, SICOS and SPOTEC bipolar devices, SiGe bipolar technology, Complementary bipolar technology and BICMOS structures. (3 Lectures)
Click Here for References

Crystal growth and Wafer manufacturing: Crystal structure, Czochralski and  FZ  growth methods, Wafer preparation and specifications, SOI Wafer manufacturing. (3 lectures)

Clean rooms, wafer cleaning and gettering: Basic concepts, manufacturing methods and equipment, Measurement methods. (3 lectures)

Photolithography:  Light sources, Wafer exposure systems, Photoresists, Baking and development,  Mask making, Measurement of mask features and defects, resist patterns and etched features.  (3 lectures)

Oxidation:  Wet and Dry oxidation, growth kinetics and models,  defects, measurement methods and characterization. (4 lectures)

Diffusion:  Models for diffused layers, Characterization methods, Segregation, Interfacial dopant pileup, oxidation enhanced diffusion, dopant-defect interaction. (4 lectures)

Ion-implantation: Basic concepts, High energy and ultralow energy implantation, shallow junction formation & modeling, Electronic stopping, Damage production and annealing, RTA Process & dopant activation.  (5 lectures)

Thinfilm Deposition: Chemical and physical vapour deposition, epitaxial growth, manufacturing methods and systems,  deposition of dielectrics and metals commonly used in VLSI,  Modeling deposition processes.  (4 lectures)

Etching Technologies: Wet etching, Plasma etching, RIE, Etching of materials used in VLSI, Modeling of etching. (4 lectures)

Back-end Technology: Contacts, Vias, Multi-level Interconnects, Silicided gates and S/D regions, Reflow & planarization, Multi-chip modules and packaging. (4 lectures)

Reference Books:

1. James Plummer, M. Deal and P.Griffin, Silicon VLSI Technology, Prentice Hall     Electronics and VLSI series, 2000.
2. Stephen Campbell,  The Science and Engineering of Microelectronics, Oxford University Press, 1996.
3. Sorab Ghandhi,  VLSI Fabrication Principles, John Wiley and Sons, 1983.
4. S.M.Sze,  VLSI Technology, McGraw-Hill, 1983.

Exam Policy and Grading:

There will be  2 Minor and 1 Major exam and an unspecified number of Assignments or surprise tests.  During the exams/tests, you are allowed to bring two A4 sheets on which you can write only formulas.  No books and class notes are permitted in the exam.

As a guideline, it may be said that the cluster of students around the class average are usually awarded a B(-) grade.

Marks Distribution:

20 %   Minor-I
20 %   Minor-II
40 %   Major
20 %  Assignments &  Surprise tests

Your feedback is valuable:

Please note that your  feedback on any aspect of this course will be greatly appreciated.  Any time, you can talk to me  to give your informal feedback. However, I will be taking two written feedbacks from you -  one just after Minor-I and the other, a week before the Major.  I expect you to be objective and enthusiastic to give your feedback.

Contact outside lecture hours:

In the department, you can find me in II-303. Phone: 1085
Email: mamidala@ieee.org



Final Pointers:

* Coming to the class on time is very essential.
* You must clarify your doubts during the lecture or at the very least immediately after the class.
* Practice solving as many problems from the text books as possible.
* Always keep a calculator with you in the class.
* Only registered students are allowed in the course.